1. Field of The Invention
The present invention relates to a technique of manufacturing a semiconductor device. More particularly, the present invention relates to a method of making a planar-type bottom electrode for semiconductor devices.
2. Description of Related Art
For applications of semiconductor devices, capacitors have been extensively used for applications related to data storage. Taking dynamic random access memory (DRAM) for example, a DRAM contains a plurality of memory unit cells for data storage. Each memory unit cell comprises a capacitor and a transistor to store data.
Planar-type capacitors are one kind of capacitor structure that is currently used. A planar-type capacitor forms bottom electrodes, dielectrics and plate electrodes in one hole of a dielectric layer. Compared with concave type capacitors, the planar-type capacitors have larger space to receive thicker dielectric (such as high-k dielectrics) and the plate electrode. Thicker dielectrics help reduce current leakage of capacitor.
Using high-k dielectrics may improve capacitance of the memory cell unit, and Equivalent Oxide Thickness (EOTs) of this kind of materials has an inverse proportional relationship to its k value. In other words, when using a dielectric with a higher dielectric constant to replace a dielectric with a lower dielectric constant, the higher dielectric may deposit a thicker film keeping the same capacitance so as to reduce the degree of current leakage.
However, with the feature size of the devices is continuously reduced to a desired size, concave type capacitors have reached their manufacturing limitations, i.e. the hole in the dielectric layer can not provide sufficient space to receive the bottom electrodes, the dielectrics and the plate electrodes.
Therefore, there is a need to provide an improved method of making capacitors to provide enough space to receive the bottom electrodes, the dielectrics and the plate electrodes to mitigate or obviate the aforementioned problems.